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Latch-up issue in CMOS Logic | Latch-up effect in VLSI - Team VLSI
SR latch outputs flipped - Electrical Engineering Stack Exchange
Latch-up or Latchup
I-V characteristic of the SCR and for the latch-up path respectively
Latch-Up Problem in CMOS – VLSI Design – Buzztech
Inner Workings of an SR Latch - YouTube
Analog IC co-design for latch-up compliance - EDN Asia